1. Field of the Invention
The present invention relates to a driving apparatus for 3-electrode plasma display panels, and more particularly, to a driving apparatus for a 3-electrode plasma display panel having a 3-electrode surface-discharge structure, the structure in which X electrode line and Y electrode line are alternately disposed parallel to one another so as to create XY electrode line pairs, address electrode lines are disposed so as to intersect the XY electrode line pairs, and display cells are defined at the intersections.
2. Background Description
FIG. 1 shows the structure of a general 3-electrode surface-discharge type plasma display panel 1, while FIG. 2 shows a display cell on the panel of FIG. 1. Referring to FIGS. 1 and 2, address electrode lines AR1 through ARm (represented by ARm), AG1 through AGm (represented by AGm), and AB1 through ABm (represented by ABm), front dielectric layer 11 and rear dielectric layer 15, Y electrode lines Y1 through and Yn, X electrode lines X1 through and Xn, a fluorescent layer 16, barrier ribs 17, and a magnesium monoxide (MgO) layer 12 as a protective membrane are provided between front glass substrate 10 and rear glass substrate 13 of the general surface-discharge type plasma display panel 1.
The address electrode lines AR1, AG1 through AGm, and ABm are disposed on the front surface of the rear glass substrate 13 in a predetermined pattern, and entirely coated with the rear dielectric layer 15. The barrier ribs 17 are formed parallel to the address electrode lines AR1, AG1 through AGm, and ABm on the front surface of the rear dielectric layer 15. The barrier ribs 17 define a discharge area on each display cell and prevent optical cross talk between display cells. The fluorescent layer 16 is formed between the barrier ribs 17.
The X electrode lines X1 through Xn and the Y electrode lines Y1, through Yn are formed on the rear surface of the front glass substrate 10 in a predetermined pattern so that they intersect the address electrode lines AR1, AG1 through AGm, and ABm at right angles. Each intersection corresponds to a display cell. To form each of the X electrode lines X1 through Xn, a transparent conductive electrode line Xna of FIG. 2, such as an indium tin oxide (ITO), is combined with a metallic electrode line Xnb of FIG. 2 to increase conductivity. Likewise, to form each of the Y electrode lines Y1 through Yn, a transparent conductive electrode line Yna of FIG. 2, such as an indium tin oxide (ITO), is combined with a metallic electrode line Ynb of FIG. 2 to increase conductivity. The X electrode lines X1 through and Xn and the Y electrode lines Y1 through and Yn are entirely coated with the front dielectric layer 11. The magnesium monoxide (MgO) layer 12 for protecting the panel 1 from a strong electric field is formed on the entire rear surface of the front dielectric layer 11. Plasma forming gas fills a discharge space 14.
FIG. 3 shows a conventional address-display separation driving method of the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 3, a unit frame is divided into 8 sub-fields SF1 through SF8 in order to achieve time-division gray level display. Each of the sub-fields SF1 through SF8 is respectively divided into an address period A1 through A8 and a display sustain period S1 through S8.
During each of the address periods A1 through A8, while a display data signal is applied to the address electrode lines AR1, AG1 through AGm, and ABm of FIG. 1, appropriate scanning pulses are sequentially applied to the Y electrode lines Y1 through Yn. During the application of the scanning pulses, if a high-level display data signal is applied to an address electrode line, wall charges are formed on a discharge cell corresponding to the address electrode line, but the other discharge cells do not gain wall charges.
In each of the display sustain periods S1 through S8, a display discharge pulse is applied to all of the X electrode lines, X1 through Xn, and all of the Y electrode lines, Y1 through Yn, in such a way that the display discharge pulse alternates between them. As a consequence, a display discharge occurs on discharge cells having wall charges formed in each of the address periods A1 through A8. As a result, the luminance of a plasma display panel is proportional to the length of the display sustain periods S1 through S8 for a unit frame. In the plasma display panel of FIG. 3, the length of the display sustaining periods S1 through S8 for a unit frame is 255T (T denotes a unit of time). Hence, a unit frame can express 256 gray levels including a zero gray level, where no display discharge occurs.
A time 1T, corresponding to 20, is set for the display sustain period S1 of the first sub-field SF1. A time 2T, corresponding to 21, is set for the display sustain period S1 of the second sub-field SF2. A time 4T, corresponding to 22, is set for the display sustain period S3 of the third sub-field SF3. A time 8T, corresponding to 23, is set for the display sustain period S4 of the fourth sub-field SF4. A time 16T, corresponding to 24, is set for the display sustain period S5 of the fifth sub-field SF5. A time 32T, corresponding to 25, is set for the display sustain period S6 of the sixth sub-field S6. A time 64T, corresponding to 26, is set for the display sustain period S7 of the seventh sub-field SF7. A time 128T, corresponding to 27, is set for the display sustain period S8 of the eighth sub-field SF8.
Accordingly, it can be seen from FIG. 3 that, when sub-fields to be displayed are appropriately selected from the 8 sub-fields, any of the selected sub-fields can display 256 gray levels including a zero gray scale, in which display discharge does not occur.
In the above-described address-display separation driving method, since the subfields SF1 through SF8 are temporally separated in a unit frame, the address period and the display sustain period are temporally separated in each of the subfields SF1 through SF8. To be more specific, in an address period, each pair of X and Y electrodes is addressed, and waits for the next operation until the other pairs of X and Y electrodes are all addressed. Consequently, the time for the address period in each subfield is lengthened, while the display sustain period is relatively shortened. This lowers the luminance of light emitted from a plasma display panel. In order to solve this problem, an address-while-display driving method as shown in FIG. 4 has been developed.
FIG. 4 shows a conventional address-while-display driving method applied to the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, a unit frame is divided into 8 subfields SF1 through SF8 in order to achieve time-division gray-scale display. The subfields overlap one another with respect to the Y electrode lines Y1 through Yn and constitute a unit frame. Hence, all of the subfields SF1 through SF8 exist at every time point and an addressing time slot is set between display discharge pulses in order to perform each addressing.
A reset step, an address step, and a display sustaining step are performed on each of the subfields, and the time allocated to each of the subfields is determined based on a display discharging time corresponding to a gray scale. If 8-bit image data display 256 gray scales per unit frame and the unit frame (generally, 1/60 sec) is divided into 255 unit periods, the first subfield SF1 driven based on the least significant bit (LSB) image data has one (20) unit period, the second subfield SF2 has 2 (21) unit periods, the third subfield SF3 has 4 (22) unit periods, the fourth subfield SF4 has 8 (23) unit periods, the fifth subfield SF5 has 16 (24) unit periods, the sixth subfield SF6 has 32 (25) unit periods, the seventh subfield SF7 has 64 (26) unit periods, and the eighth subfield SF8, driven based on the most significant bit (MSB) of the image data, has 128 (27) unit periods. That is, since the sum of the unit periods allocated to the subfields is 255 unit periods, 255 gray scales can be displayed. If no discharge on any subfield is included, 256 gray scales can be displayed.
FIG. 5 shows a general driving apparatus for the plasma display panel of FIG. 1. Referring to FIG. 5, the general driving apparatus for the plasma display panel 1 of FIG. 1 includes an image processor 66, a logic controller 62, an address driver 63, an X-driver 64, and a Y-driver 65. The image processor 66 converts an external analog image signal into a digital signal and generates an internal image signal, for example, 8-bit red (R) image data, 8-bit green (G) image data, 8-bit blue (B) image data, a clock signal, and vertical and horizontal synchronous signals. The logic controller 62 generates driving control signals SA, SY, and SX according to the internal image signal received from the image processor 66. The address driver 63 processes the address signal SA out of the driving control signals SA, SY, and SX to obtain a display data signal, and applies the display data signal to address electrode lines. The X-driver 64 processes the X driving control signal SX out of the driving control signals SA, SY, and SX and applies the resultant signal to X electrode lines. The Y-driver 65 processes the Y driving control signal SY out of the driving control signals SA, SY, and SX and applies the resultant signal to Y electrode lines.
FIG. 6 shows driving signals applied to a unit subfield on the panel of FIG. 1 by the address-display separation driving method of FIG. 3. Referring to FIG. 6, reference character SAR1 . . . ABm denotes a driving signal applied to the address electrode lines AR1 through ARm, AG1 through AGm, and AB1 through ABm of FIG. 1. Reference character SX1 . . . Xn denotes a driving signal applied to the X electrode lines X1 through Xn of FIG. 1, and reference characters SY1 through and SYn denote a driving signal applied to the Y electrode lines Y1 through Yn of FIG. 1, respectively. FIG. 7 shows wall charges distributed on a display cell at the point in time immediately after a gradual rising voltage is applied to the Y electrode lines Y1 through Yn during a reset period PR of FIG. 6. FIG. 8 shows wall charges distributed on a display cell when the reset period PR of FIG. 6 terminates. Referring to FIG. 6, during the reset period PR of a unit subfield SF, first, the driving voltage SX1 . . . Xn continuously increases from a ground voltage VG to a second voltage VS, for example, 155 V. At this time, the ground voltage VG is applied to the Y electrode lines Y1, through Yn and the address electrode lines AR1, AG1 through AGm, and ABm. Accordingly, while a weak discharge occurs between the X electrode lines X1 through Xn and the Y electrode lines Y1 through Yn and between the X electrode lines X1 through Xn and the address electrode lines AR1 to ABm, negative wall charges are formed around the X electrode lines X1 through Xn.
Next, the driving voltages SY1 through SYn continuously increase from the second voltage Vs, for example, 155 V, to the highest voltage (VSET+VS), for example, 355 V. The voltage (VSET+VS) is obtained by adding a third voltage VSET to the second voltage VS. While the voltages SY1 through SYn increase from the second voltage to the highest voltage, the ground voltage VG is applied to the X electrode lines X1 through Xn and the address electrode lines AR1 to ABm. Accordingly, a weak discharge occurs between the X electrode lines and the Y electrode lines, and a weaker discharge occurs between the Y electrode lines and the address electrode lines. The discharge between the X electrode lines and the Y electrode lines is stronger than the discharge between the Y electrode lines and the address electrode lines, because negative wall charges have been formed around the X electrode lines. Consequently, many negative wall charges are formed around the Y electrode lines, positive wall charges are formed around the X electrode lines, and a few positive wall charges are formed around the address electrode lines, as shown in FIG. 7.
After the voltage increases from VS to (VSET+VS), while the driving voltage SX1 . . . Xn is maintained at the second voltage VS, the driving voltages SY1, through SYn continuously decreases from the second voltage VS to the ground voltage VG. At this time, the ground voltage VG is applied to the address electrode lines AR1, AG1 through AGm, and ABm. Accordingly, due to a weak discharge between the X electrode lines and the Y electrode lines, some of the negative wall charges around the Y electrode lines move toward the X electrode lines, as shown in FIG. 8. Also, due to the ground voltage VG being applied to the address electrode lines, the number of positive wall charges around the address electrode lines slightly increases.
Accordingly, during the subsequent address period PA, smooth addressing can be performed as a display data signal is applied to the address electrode lines, and the Y electrode lines biased to a fourth voltage VSCAN, which is lower than the second voltage VS, are sequentially subject to a scanning signal with the ground voltage VG. If a display cell is selected, a display data signal with positive address voltage VA is applied to the address electrode lines. Otherwise, a display data signal with the ground voltage VG is applied to the address electrode lines. Accordingly, when a display data signal with the positive address voltage VA is applied while a scanning pulse with the ground voltage VG is applied, wall charges are formed on a corresponding display cell due to address discharge, but no wall charges are formed on the other display cells. At this time, in order to achieve more accurate and efficient address discharge, the second voltage VS is applied to the X electrode lines.
Subsequently, during the display sustaining period PS, a display sustaining pulse with the second voltage VS is applied to each of the X electrode lines and each of the Y electrode lines in such a way that the display sustaining pulse alternates between them. Thus, a discharge for sustaining the display occurs on display cells having wall charges formed during the address period PA.
FIG. 9 shows a structure of a conventional Y-driver of a driving apparatus for applying the driving signals of FIG. 6. Referring to FIGS. 6 and 9, the conventional Y-driver includes a reset/sustaining circuit RSC, a scan driving circuit AC, and a switching output circuit SIC. The reset/sustaining circuit RSC generates driving signals to be applied to the Y electrode lines during the reset period PR and the display sustaining period PS. The scan driving circuit AC generates driving signals to be applied to the Y electrode lines during the addressing period PA. In the switching output circuit SIC, upper transistors YU1 through YUn and lower transistors YL1 through YLn are disposed to create upper transistor/lower transistor pairs, and the common output lines of the upper transistor/lower transistor pairs are connected to the Y electrode lines Y1 through Yn of the 3-electrode plasma display panel 1. The operation of the Y-driver of FIG. 9 will now be described with reference to FIGS. 6 and 9.
During the reset period PR and the display sustaining period PS, the driving signals ORS from the reset/sustaining circuit RSC are applied to the Y electrode lines of the 3-electrode plasma display panel 1 via a point A in the scan driving circuit AC and the lower transistors YL1 through YLn in the switching output circuit SIC. At this time, all large power transistors SSC1, SSC2, SSP, and SSCL in the scan driving circuit AC are turned off. The driving signals ORS from the reset/sustaining circuit RSC are applied to the Y electrode lines of the 3-electrode plasma display panel 1 via the point A and the third large power transistor SSP in the scan driving circuit AC and the upper transistors YU1 through YUn in the switching output circuit SIC. At this time, the large power transistors SSC1, SSC2, and SSCL excluding the third large power transistor SSP in the scan driving circuit AC are turned off.
During the address period PA, the large power transistors SSC1, SSC2, and SSCL excluding the third large power transistor SSP in the scan driving circuit AC are turned on. A scan bias voltage VSCAN is applied via the first large power transistor SSC1 and second large power transistors SSC2 to the upper transistors YU1 through YUn of the switching output circuit SIC. The ground voltage VG (FIG. 6) is applied to the lower transistors YL1 through YLn of the switching output circuit SIC via the fourth large power transistor SSCL. In this case, the lower transistor connected to a Y electrode line to be scanned is turned on, while the upper transistor connected to the Y electrode line to be scanned is turned off. The lower transistors connected to the other Y electrode lines not to be scanned are turned off, while the upper transistors connected to the Y electrode lines not to be scanned are turned on. The scan ground voltage VG is then applied to the Y electrode line to be scanned, and the scan bias voltage VSCAN is applied to the other Y electrode lines not to be scanned.
During the addressing period PA, when the scan ground voltage VG is applied to the Y electrode line to be scanned, current from the display cells (electrical capacitors) connected to the Y electrode line to be scanned passes through a lower transistor in the switching output circuit SIC and the fourth large power transistor SSCL in the scan driving circuit AC and then flows to a ground terminal.
During the addressing period PA, when a display data signal is applied to the address electrode lines, discharge current from the address electrode lines to which a selection voltage VA has been applied flows to an Y electrode line that is being scanned. At this time, current sequentially passes through the other Y electrode lines not being scanned, the upper transistors of the switching output circuit SIC, and the first and second large power transistors SSC1 and SSC2 in the scan driving circuit AC and then flows to the terminal of the scan bias voltage VSCAN.
During the addressing period PA, at the point in time when the application of the display data signal to the address electrode lines AR1, AG1 through AGm, and ABm terminates, current from the terminal of the scan bias voltage VSCAN passes through the first and second large power transistors SSC1 and SSC2 in the scan driving circuit AC, the upper transistors of the switching output circuit SIC, and the Y electrode lines and then flows to the address electrodes AR1, AG1 through AGm, and ABm.
During the addressing period PA, at the point in time when the application of the scan ground voltage VSCAN to the one Y electrode line to be scanned terminates, current from the terminal of the scan bias voltage VSCAN passes through the first and second large power transistors SSC1 and SSC2 in the scan driving circuit AC, the upper transistors of the switching output circuit SIC, and the Y electrode lines and then flows to the display cells (electrical capacitors).
Accordingly, it can be seen that large power transistors for switching must be connected between the common line of the upper transistors in the SIC and the terminal of the scan bias voltage VSCAN. When only one large power transistor SSC1 or SSC2 is connected, the following two problems are generated.
Firstly, if only the second large power transistor SSC2 is connected, the driving signals ORS from the reset/sustaining circuit RSC are applied to the terminal of the scan bias voltage VSCAN via the internal diode of the second large power transistor SSC2 during the reset period PR and the display sustaining period PS, such that current flows. As a result, driving during the reset period PR and the display sustaining period PS is unstable, and power consumption increases.
Secondly, if only the first large power transistor SSC1 is connected, an unexpected over-shoot pulse from the reset/sustaining circuit RSC can be applied to the upper transistors YU1 through YUn of the switching output circuit SIC through the internal diode of the first large power transistor SSC1. As a result, driving during each of the periods may be unstable. For these reasons, two large power transistors SSC1 and SSC2 are needed.
If the upper and lower common lines are simply disconnected because of absence of the third large power transistor SSP, the driving signals ORS from the reset/sustaining circuit RSC are applied to all of the Y electrode lines Y1 through Yn through the lower transistors YL1 through YLn of the SIC during the reset period PR and the display sustaining period PS, and also applied to the first large power transistor SSC1 through the internal diodes of the upper transistors and the second large power transistor SSC2 in the scan driving circuit AC. As a result, the performance of the first large power transistor SSC1 can be degraded, and the durability shortened. However, if the third large power transistor SSP exists, a predetermined voltage drops to the third large power transistor SSP. Thus, a voltage applied to the first large power transistor SSC1 can be lowered.
As described above, a conventional apparatus for driving a 3-electrode plasma display panel has a deficiency in that the scan driving circuit AC of a Y driver requires four expensive large power transistors SSC1, SSC2, SSP, and SSCL.